1. Field of the Invention
The present invention relates to a load short-circuit state and load open state detection circuit, and more particularly to a circuit for detecting a short-circuit state and an open state of an inductive load such as a magnetic head and the like.
2. Related Art
FIG. 1 shows an arrangement of a conventional load short-circuit state and load open state detection circuit. The detection circuit shown in FIG. 1 comprises an H-bridge type load driver comprised of NPN transistors Q1 through Q4 and a circuit for detecting the short-circuit state and the open state of an L-type (an inductive type) load connected to the driver.
Terminals 2, 3, 7 and 8 are respectively connected to the bases of the NPN transistors Q1 through Q4 for receiving driving signals for AC-driving the L-type load. The collectors of the transistors Q1 and Q3 are connected to a terminal 1 to which a power supply voltage Vcc is applied. An emitter of the transistor Q3 is connected to a collector of the transistor Q4. Emitters of the transistors Q2 and Q4 are connected to a constant current source 9. Emitters of the transistors Q1 and Q3 are connected to an X terminal 4 and a Y terminal 6, respectively. An L-type load is connected between the X and Y terminals 4 and 6. The L-type load is represented by a series circuit of an inductance LH and a resistor RH. The X terminal 4 is connected to an input terminal of a clamp circuit 18.
An output terminal of the clamp circuit 18 is connected to a base of an NPN transistor Q8. A collector of the NPN transistor Q8 is connected to the Vcc terminal 1, and an emitter of the transistor Q8 is grounded through a capacitor C1. A constant current source 16 and an inverted input terminal of a comparator 12 are connected to a node between the emitter of the transistor Q8 and the capacitor C1. A reference voltage VREF is applied to a non-inverted input terminal of the comparator 12. An output terminal of the comparator 12 is connected to an output terminal 13.
An operation of the detection circuit shown in FIG. 1 will now be described with reference to FIGS. 2A through 2L, 3A through 3L, and 4A through 4L. FIGS. 2A through 2L show waveforms of various components when the load is in a normal state. FIGS. 3A through 3L show waveforms of various components when the load is short-circuited (the X terminal 4 and the Y terminal 6 are short-circuited). FIGS. 4A through 4L show waveforms of various components when the load is in an open state (the X terminal 4 and the Y terminal 6 are electrically isolated).
An operation of the detection circuit shown in FIG. 1 will first be described with reference to FIGS. 2A through 2L when the load is in the normal state.
Drive signals shown in FIGS. 2A through 2D are applied to the input terminals 2, 3, 7, and 8, respectively for AC-driving the L-type load. When the drive signals are not applied to the input terminals 2, 3, 7, and 8 as at time t0, for example, the transistors Q1 through Q4 are cut off so that the currents IC1 and IC4 flowing into the transistors Q1 and Q4 are "0" as shown in FIGS. 2E and 2F current IW flowing into the load is also "0". Furthermore, the capacitor C1 is not charged so that a voltage across the capacitor C1 is "0" and a relation between an input voltage VC1 of the inverted terminal of the comparator 12 and the reference voltage VREF is VC1&lt;VREF as shown in FIG. 2J. Accordingly, the output of the comparator 12 and the voltage of the output terminal 13 are both at an H (High) level, as shown in FIGS. 2K and 2L, respectively.
At time t1, a H-level drive signal is applied to the input terminals 2 and 8 as shown in FIGS. 2A and 2D as shown in FIGS. 2A and 2D, respectively. Furthermore, an L-level drive signal is applied to the input terminals 3 and 7 as shown in FIGS. 2B and 2C, respectively. Accordingly, the NPN transistors Q1 and Q4 are saturated and the NPN transistors Q2 and Q3 are cut off. For this reason, the currents IC1 and IC4 shown in FIGS. 2E and 2F flow into the transistors Q1 and Q4, respectively and the current IW shown in FIG. 2G flows into the load. Each of the values of currents IC1, IC4, and IW equals to a value of a current flowing into a constant current source 9.
At time t2, the L-level drive signal is applied to the input terminals 2 and 8 as shown in FIGS. 2A and 2D, respectively. Furthermore, the H-level drive signal is applied to the input terminals 3 and 7 as shown in FIGS. 2B and 2C, respectively. Accordingly, the NPN transistors Q1 and Q4 are cut off and the NPN transistors Q2 and Q3 are saturated. For this reason, the currents IC2 and IC3 flow into the NPN transistors Q2 and Q3, respectively and the current IW shown in FIG. 2G flows into the load. Each of absolute values of the currents IC2, IC3, and IW equals to the value of the current I0 flowing into the constant current source 9.
At time t1, when the current IW flows into the inductance LH of the load, a counter electromotive force VH is generated at the X terminal 4 as shown in FIG. 2H. This counter electromotive force VH is represented in the following equation: EQU VH=RH.times.IW'/ (1-e.sup.-(RH/LH)t) (1)
wherein IW'- is a load current IW when t hours has elapsed from time t1; and t- is a time which has elapsed from the time t1. If RH=10 .OMEGA., LH=5 .mu.H, IW'=1 mA, and t=1 nS, then VH=5.0 V. A voltage VX including the counter electromotive force VH is supplied to the clamp circuit 18.
The clamp circuit 18 outputs a reference voltage VCL when the input signal VX is larger than a reference level VCL and outputs the input signal VX when the input signal VX is smaller than the reference level VCL. An output signal of the clamp circuit 18 is applied to the base of the NPN transistor Q8. At the time t1, the emitter voltage VC1 of the NPN transistor Q8 is represented by the following equation: EQU VC1=VCL-VBEQ8 (2)
wherein VBEQ8 is a base-emitter forward voltage of the NPN transistor Q8.
Since the VBEQ8 is constant, a change VCL' of the voltage VC1 to be applied to the capacitor C1 amounts to the VCL. At this time, the VC1 is larger than the reference voltage VREF as shown in FIG. 2J so that the voltages of the output of the comparator 12 and the output terminal 13 is at the L level as shown in FIGS. 2K and 2L, respectively.
The counter electromotive force VH decreases with the elapse of the time and the output of the clamp circuit 18 becomes smaller than the charging voltage VC1 of the capacitor C1 when VX (=VH)&lt;VCL is satisfied so that the NPN transistor Q8 is cut off. Further, the inverted input terminal of the comparator 12 is connected to the constant current source 16 so that the VC1 is gradually decreased. The time constant .tau. of the decrease is represented by the following equation (3): EQU .tau.=C1.multidot.(VCL'-VREF)/I1 (3)
wherein I1 is a value of a current flowing into the constant current source 16.
As described above, when the drive signals are applied to the input terminals 2, 3, 7, and 8, the voltage of the output terminal 13 changes from the H level to the L level. Accordingly, it can be determined that the load connected between the X terminal 4 and the Y terminal 6 is normal.
An operation of the detection circuit shown in FIG. 1 when the load is short-circuited will now be described with reference to FIGS. 3A through 3L.
At time t1, the H-level drive signal is applied to the input terminals 2 and 8 as well as the L-level drive signal is applied to the input terminals 3 and 7 as shown in FIGS. 3A through 3D. For this reason, the NPN transistors Q1 and Q4 are saturated so that the currents IC1, IC4 and IW flow as shown in FIGS. 3E through 3G. However, the load is short-circuited so that the counter electromotive force VH is not generated as shown in FIG. 3H.
Accordingly, the output of the clamp circuit 18 is at the L level as shown in FIG. 3I so that the base voltage of the NPN transistor Q8 is at the L level. For this reason, the condition VC1&lt;VREF is satisfied as shown in FIG. 3J so that the output of the comparator 12 and the output terminal 13 are at the H level as shown in FIGS. 3K and 3L.
As described above, even if the drive signals are applied to the input terminals 2, 3, 7, and 8, the voltage of the output terminal 1 is remained at the H level. Accordingly, it can be determined that the load connected between the X terminal 4 and the Y terminal 6 is in an abnormal state.
An operation of the detection circuit shown in FIG. 1 when the load is in the open state will now be described with reference to FIGS. 4A through 4L.
At time t1, the H-level drive signal is applied to the input terminals 2 and 8 and the L-level drive signal is applied to the input terminals 3 and 7 as shown in FIGS. 4A through 4D. For this reason, the NPN transistors Q1 and Q4 are saturated. However, since the load is in the open state, no load current IW flows. For this reason, the currents IC1 and IW are "0" as shown in FIGS. 4E and 4G, respectively. It is to be noted that a current flows into the NPN transistor Q4 through the NPN transistor Q3 and the waveform of the current is as shown in FIG. 4F. Furthermore, since the load is in the open state, the counter electromotive force is not generated as shown in FIG. 4H.
At time t2, the L-level drive signal is applied to the input terminals 2 and 8 and the H-level drive signal is applied to the input terminals 3 and 7 as shown in FIGS. 4A through 4D. For this reason, the NPN transistors Q1 and Q4 are cut off. Since the load is in the open state, no load current IW flows. As a result, the currents IC1, IC4, and IW are "0" as shown in FIGS. 4E through 4G, respectively. Furthermore, since the load is in the open state, the counter electromotive force VH is not generated as shown in FIG. 4H.
Accordingly, the output of the clamp circuit 18 is at the L level as shown in FIG. 4I so that the base voltage of the NPN transistor Q8 is at the L level. For this reason, the condition VC1&lt;VREF is satisfied as shown in FIG. 4J so that the output of the comparator 12 and the voltage of the output terminal 13 remain at the H level as shown in FIGS. 4K and 4L, respectively.
As described above, even if the drive signal is applied to the input terminals 2, 3, 7, and 8, the voltage of the output terminal 13 remain at the H level so that it can be determined that the load connected between the X terminal 4 and the Y terminal 6 is in the abnormal state.
In order for the load state detection circuit operate normally, .tau. in equation (3) and the period T of the drive signal to be applied to the input terminals 2, 3, 7, and 8 must have relation of .tau.&gt;T. When the time constant .tau. is small, the condition VC1&lt;VREF is established during an interval of time t0 to time t2 so that the output of the comparator 12 is at the H level. As a result, the voltage of the output terminal 13 also turns at the H level which is identical to the output in the load short-circuited state and in the load open state.
As is apparent from the equation (3), the time constant .tau. depends on the changed amount VCL' of the voltage on the premise that the values of C1, VREF, and I1 are constant.
If the inductance LH connected to the X terminal 4 and the Y terminal 6 is assumed to be 1 .mu.H, RH=10 .OMEGA., LH 1 .mu.H, IW'=1 mA, and t=1 nS, then VH=1.0 V. If the clamp voltage VCL of the clamp circuit 18 is set corresponding to the counter electromotive force VH (=5.0 V) at LH=5 .mu.H, namely VCL=3.0 V, the counter electromotive force VH at LH =1 .mu.H is not clamped so that the voltage VC1 at time t1 is VC1=VH-VBEQ8. Since VBEQ8 is constant, the changed amount VCL' of the voltage to be applied to the capacitor C1 is VH (=1.0 V). On the other hand, if LH=5 .mu.H and VH=5.0 V, the changed amount of the voltage to be applied to the capacitor C1 is 3.0 V (=VCL).
Accordingly, if C1=10 pF, I1=20 .mu.A, VREF=0.5 V and VLC=3.0 V, .tau. at LH=5 .mu.H and LH=1 .mu.H is represented in the following equations: EQU .tau.(LH=5 .mu.H)=(10 pF.multidot.(3.0 V-0.5 V)/20 .mu.A=1.25 .mu.S EQU .tau.(LH=1 .mu.H)=(10 pF.multidot.(1.0 V-0.5 V)/20 .mu.A=0.25 .mu.S
As mentioned above before, in order for the load state detection circuit operate normally, .tau.&gt;T must be satisfied. Accordingly, a frequency f of a signal to be applied to the input terminals 2, 3, 7, and 8 may be 800 KHz or more at LH=5 .mu.H but must be 4 MHz or more at LH=1 .mu.H.
As described above, according to the conventional load-state detection circuit shown in FIG. 1, a problem is posed that the allowable frequency range of the drive signal to be applied to the input terminals 2, 3, 7, and 8 is changed depending on the value of the inductance LH of the load.